1. Technical Field
Various embodiments of the present disclosure generally relate to a semiconductor memory apparatus, and more particularly, to a circuit and method controlling a refresh period in a semiconductor memory apparatus.
2. Related Art
A dynamic random access memory (DRAM), as one of semiconductor memories, has a memory cell consisting of a single cell transistor and a single cell capacitor. The DRAM cell is volatile in nature in that data stored in its cell capacitor—a state of high or low level—cannot be retained unless power is not supplied.
Even with a constant power supply, a DRAM cell is incapable of retaining data in the cell capacitor due to leakage factors such as leakage currents. Thus, an extra operation, i.e., a refresh operation, should be provided to periodically re-write data into the DRAM cell for continuous retention of data.
For such functionalities, a DRAM is generally equipped with a refresh control circuit to control the refresh operation. This refresh control circuit generates a refresh signal that is activated (oscillates or toggles) in a predetermined cycle. Meanwhile, a high temperature typically adversely affects the data retention capability of a semiconductor memory cell because the threshold voltage of the cell transistor goes down as temperature rises. But, data retention capability of a semiconductor memory cell is enhanced in a low temperature, because a threshold voltage of the cell transistor becomes higher in proportion to a drop of temperature. For that reason, a refresh control circuit is typically designed to reduce the activation cycle of the refresh signal (a refresh cycle, which is the interval between refresh operations) as temperature rises, or to extend the refresh cycle as temperature drops.
Typical refresh control circuits are configured considering only room temperature as a variable (typically, 0° C.-100° C.). While a refresh cycle linearly varies in room temperatures between 0° C. to 100° C., in temperature conditions outside the range of room temperature (0° C.-100° C.), the refresh cycles are set to fixed values, without adaptive variations. As a result, when a DRAM is operating under cool temperature (typically, under 0° C.), current dissipation inadvertently occurs due to an improper refresh cycle that is shorter than needed. On the other hand, when a DRAM is operating under hot temperature (typically, over 100° C.), an excessively long refresh cycle results in data loss.